Validation of Executable Application Models Mapped onto Network-on-Chip Platforms

Sanna Määttä; Leandro Soares Indrusiak; Luciano Ost; Leandro Moller; Jari Nurmi; Manfred Glesner; Fernando Moraes

doi:10.1109/SIES.2008.4577689

Validation of Executable Application Models Mapped onto Network-on-Chip Platforms

Sanna Määttä, Leandro Soares Indrusiak, Luciano Ost, Leandro Moller, Jari Nurmi, Manfred Glesner, Fernando Moraes

Computer Science

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Due to the increasing design size, complexity, and heterogeneity of today's embedded systems, designers need novel design methods in order to validate application-specific functionality together with different platform implementation alternatives. Ideally, this should happen at as early stage of the design process as possible, so that designers can explore the design space before they have to commit to specific processor architectures or custom hardware implementation. This paper takes advantage of the hierarchical design style and the support for heterogeneous Models of Computation (MoC) existing in actor-oriented frameworks and presents a methodology for modelling and validation of multiprocessor embedded systems. The proposed methodology is fully model-based, with different modelling styles for the application and the underlying implementation platform. In this paper we focus on the validation of applications modelled using Ptolemy II actors and UML sequence diagrams, mapped onto multiprocessor Network-on-Chip (NoC) platforms. We also present a case study, where one executable application model is mapped onto different NoC topologies, and show the simulation results for communication latency of each alternative.

Original language	English
Title of host publication	Int Symposium on Industrial Embedded Systems
Place of Publication	New York
Publisher	IEEE
Pages	118-125
Number of pages	8
ISBN (Print)	978-1-4244-1994-4
DOIs	https://doi.org/10.1109/SIES.2008.4577689
Publication status	Published - 2008

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10.1109/SIES.2008.4577689

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title = "Validation of Executable Application Models Mapped onto Network-on-Chip Platforms",

abstract = "Due to the increasing design size, complexity, and heterogeneity of today's embedded systems, designers need novel design methods in order to validate application-specific functionality together with different platform implementation alternatives. Ideally, this should happen at as early stage of the design process as possible, so that designers can explore the design space before they have to commit to specific processor architectures or custom hardware implementation. This paper takes advantage of the hierarchical design style and the support for heterogeneous Models of Computation (MoC) existing in actor-oriented frameworks and presents a methodology for modelling and validation of multiprocessor embedded systems. The proposed methodology is fully model-based, with different modelling styles for the application and the underlying implementation platform. In this paper we focus on the validation of applications modelled using Ptolemy II actors and UML sequence diagrams, mapped onto multiprocessor Network-on-Chip (NoC) platforms. We also present a case study, where one executable application model is mapped onto different NoC topologies, and show the simulation results for communication latency of each alternative.",

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AU - Määttä, Sanna

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AU - Ost, Luciano

AU - Moller, Leandro

AU - Nurmi, Jari

AU - Glesner, Manfred

AU - Moraes, Fernando

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N2 - Due to the increasing design size, complexity, and heterogeneity of today's embedded systems, designers need novel design methods in order to validate application-specific functionality together with different platform implementation alternatives. Ideally, this should happen at as early stage of the design process as possible, so that designers can explore the design space before they have to commit to specific processor architectures or custom hardware implementation. This paper takes advantage of the hierarchical design style and the support for heterogeneous Models of Computation (MoC) existing in actor-oriented frameworks and presents a methodology for modelling and validation of multiprocessor embedded systems. The proposed methodology is fully model-based, with different modelling styles for the application and the underlying implementation platform. In this paper we focus on the validation of applications modelled using Ptolemy II actors and UML sequence diagrams, mapped onto multiprocessor Network-on-Chip (NoC) platforms. We also present a case study, where one executable application model is mapped onto different NoC topologies, and show the simulation results for communication latency of each alternative.

AB - Due to the increasing design size, complexity, and heterogeneity of today's embedded systems, designers need novel design methods in order to validate application-specific functionality together with different platform implementation alternatives. Ideally, this should happen at as early stage of the design process as possible, so that designers can explore the design space before they have to commit to specific processor architectures or custom hardware implementation. This paper takes advantage of the hierarchical design style and the support for heterogeneous Models of Computation (MoC) existing in actor-oriented frameworks and presents a methodology for modelling and validation of multiprocessor embedded systems. The proposed methodology is fully model-based, with different modelling styles for the application and the underlying implementation platform. In this paper we focus on the validation of applications modelled using Ptolemy II actors and UML sequence diagrams, mapped onto multiprocessor Network-on-Chip (NoC) platforms. We also present a case study, where one executable application model is mapped onto different NoC topologies, and show the simulation results for communication latency of each alternative.

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EP - 125

BT - Int Symposium on Industrial Embedded Systems

PB - IEEE

CY - New York

ER -

Validation of Executable Application Models Mapped onto Network-on-Chip Platforms

Abstract

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