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Future microprocessor trends appear to be dominated by complexity, power density, hot spots, and wire scaling concerns – issues which can only be aggravated with design migration into extreme low-nanometre processes. Alternative microarchitectures are therefore of great interest. This paper presents an evaluation of the hardware cost of a Superscalar Stack Operand Store, using a 90nm standard cell library as a reference model and explores various look-ahead configurations for issue widths up to 4-wide.elements of ASIC layout, RC extraction, and timing simulation are considered, and results presented in absolute and FO4 based timing measures. Lookahead schemes are projected to offer up to 60% performance gain for cycle times in the analysis presented.
|Publication status||Unpublished - 1 Jan 2016|
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