By the same authors

WCET preserving hardware prefetch for Many-Core real-time systems

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Published copy (DOI)

Author(s)

Department/unit(s)

Publication details

Title of host publicationACM International Conference Proceeding Series
DatePublished - 8 Oct 2014
Pages193-202
Number of pages10
PublisherAssociation for Computing Machinery (ACM)
Original languageEnglish
ISBN (Print)9781450327275

Abstract

There is an obvious bus bottleneck when multiple CPUs within a Many-Core architecture share the same physical offchip memory (eg. DDR/DRAM). Worst-Case Execution Time (WCET) analysis of application tasks will inevitably include the effects of sharing the memory bus amongst CPUs; likewise average case execution times will include effects of individual memory accesses being slowed by interference with other memory requests from other CPUs. One approach for mitigating this is to use a hardware prefetch to move instructions and data from memory to the CPU cache before a cache miss instigates a memory request. However, in a real-time system, there is a trade-off between issuing prefetch requests to off-chip memory and hence reducing bandwidth available to serving CPU cache misses; and the gain in the fact that some CPU cache misses are avoided by the prefetch with the memory system seeing reduced memory requests. In this paper we propose, analyse and show the implementation of a hardware prefetcher designed so that WCET of application tasks are not affected by the run-time behaviour of the prefetcher, i.e. it utilises spare time within the memory system to issue prefetch requests and forward them to the appropriate CPU. As well as not affecting WCET times, the prefetcher enables significant reduction in average case execution times of application tasks, showing the efficacy of the approach.

Discover related content

Find related publications, people, projects, datasets and more using interactive charts.

View graph of relations