By the same authors

XL-STaGe: A Cross-Layer Scalable Tool for Graph Generation, Evaluation and Implementation

Research output: Contribution to conferencePaper

Author(s)

Department/unit(s)

Conference

ConferenceInternational Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XVI)
CountryGreece
CitySamos
Conference date(s)17/07/1620/07/16

Publication details

DatePublished - 19 Jan 2017
Number of pages6
Original languageEnglish

Abstract

This paper presents XL-STaGe, a cross-layer tool for traffic-inclusive directed acyclic graph generation and implementation. In contrast to other graph-generation tools which focus on high-level DAG models, XL-STaGe consists of a set of processes that generate the task-graphs as well as a detailed process model for each node in each graph. The tool is highly customizable, with many parameters that can be tuned to meet the user’s requirements to control the topology, connection density, degree of parallelism and duration the task-graph. Moreover, two use cases are presented, a high-level one, which illustrate the benefit of the developed tool in application mapping and a circuit-level one to verify the accuracy of the XL-STaGe process models when implemented in hardware.

    Research areas

  • network traffic, graceful, Many-Core, traffic modelling, optimisation

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